Content addressable memory (CAM) arrays are commonly used in cache systems, and other address translation systems, of high speed computing systems. They are also useful in high-speed network routers, and many other applications known in the art of computing.
The CAM arrays typically are comprised of a plurality of rows, each row having multiple CAM blocks and each CAM block has plurality of CAM cells. The CAM arrays are characterized by circuitry capable of generating a “local match” output for each CAM block in a row and a “global match” output for each row of CAM blocks in the CAM arrays indicating whether any location of the array contains a data pattern matching a query input and the identity of that location. Each CAM cell of a CAM array typically has the ability to store a unit of data, and the ability to compare that unit of data with a unit of a query input. Each CAM block has the ability to generate the local match output. A compare result indication of each CAM block, which is a local match (LMAT) signal, in a row is combined to produce a global match (GMAT) signal for the row to indicate whether the row of CAM cells contains a stored word matching a query input. The GMAT signals from each row in the CAM array together constitute global match output signals of the array; these signals may be encoded to generate the address of matched locations or used to select data from rows of additional memory.
Each CAM cell in each CAM block of each column in the CAM array is typically connected to a common write bit line. The common write bit line is used to read and write the data from/to a memory cell, which are selected using a generated address.
Further, each CAM cell in each CAM block of each column in the CAM arrays are typically connected to a common query data line, also referred to as a common compare data line. The common compare data line allows enabling simultaneous data searching in each CAM cell in a column from a query input. The common compare data line can also be used as a write data line.
The unit of data stored in a CAM array cell is often binary, having two possible states: logic one, and logic zero. The CAM blocks of these arrays produce a local match compare result if the query input is equal to the data stored in the CAM cells in the CAM blocks, and a mismatch result otherwise. Whereas, TCAM (ternary CAM) cells can store three states: logic one, logic zero, and don't care. TCAM blocks of these TCAM arrays produce a local match compare result if the query input is either equal to the data stored in the CAM cells in the TCAM blocks, the query input contains a don't care state, or the data stored is a don't care data. The TCAM arrays produce a mismatch result otherwise. The TCAM arrays are particularly useful in address translation systems that allow variably sized allocation units.
As described above, in a conventional CAM array, each of the TCAM cells in a CAM block is connected to an associated LMAT line. Each LMAT line is connected to an associated GMAT line in a row via a GMAT evaluation transistor. Further, each CAM block includes a conversion circuit, which performs the LMAT to GMAT signal conversion and preconditioning of the LMAT and GMAT lines. Each conversion circuit includes an LMAT precharge transistor that is connected between a supply voltage VDD and the associated LMAT line, a GMAT evaluation transistor that is connected between the supply voltage VDD and the GMAT associated line, and a GMAT predischarge transistor that is connected between the GMAT line and ground.
Before a search cycle, the LMAT line is kept at a logic high voltage and the GMAT line is kept at a logic low voltage. When a TCAM cell is queried, if there is a mismatch between a stored word and a compare word, the LMAT line is discharged to a logic low voltage via the TCAM cell. If there is no mismatch between the stored word and the compare word then the LMAT line remains at a logic high voltage. If at lest one of the LMAT lines in a row is discharged due to a mismatch, the corresponding GMAT line is evaluated to a logic high voltage. If all the LMAT lines in a row remain at a logic high voltage indicating a match, then the associated GMAT line remains in the logic low voltage. Before the start of a next search cycle, the LMAT line, which may go to a logic low voltage due to the mismatch, has to be precharged back to a logic high voltage and the associated GMAT line has to be predischarged to a logic low voltage. During the precharge operation, if the GMAT predischarge transistor is enabled and if any of the associated LMAT lines are still at the logic low voltage, then there will be a direct path from the VDD to ground via the GMAT evaluation transistor and the GMAT predischarge transistor, such a path is commonly referred to as a “crowbar” path, which can result in significant power consumption for each mismatch condition, a large crowbar current can occur which can result in large surges.
Further, as the number of CAM cells in each CAM block of a CAM array increases; capacitive loading on the match lines increases accordingly. As loading on the match lines increases, the current required to charge the match lines toward the supply voltage increases. Accordingly, as CAM words are widened, for example, to accommodate longer Internet addresses, power consumption resulting from charging the match lines during compare operations may significantly increase.
In order to avoid the crowbar path, in the conventional CAM array, the precharge sequencing is generally performed using a fixed delay between the pre-charging of the LMAT line and the GMAT line on a row-by-row basis. Using such a fixed delay assures that the GMAT is precharged only after an associated LMAT line is precharged. Generally, such fixed delays are designed for use in large CAM array configurations because the fixed delay has to be increased as the GMAT line length increases. Further, as the number of columns in the CAM array increases due to an increase in the number of bits to be stored in the TCAM cells, the LMAT line and the GMAT line length also increases. This necessitates using a very high fixed delay to accommodate for a large CAM configuration that can be required in a compiler memory.
Using such a high fixed delay can result in an increased cycle time and a significant reduction in performance. Especially when using smaller CAM array configurations in compiler memories, since the same control block having the high fixed delay is used for all compiler memory configurations.
Typically, to precharge a large GMAT line, a large precharge transistor device is required. However, using such a large precharge transistor device can be inefficient for large CAM array configurations.
In addition, in a conventional CAM array, GMAT predischarge transistors are located at one end of each row in the CAM array. To precharge the GMAT lines, large GMAT precharge drivers are used at the end of long GMAT lines (Resistor-Capacitance line). Using such large GMAT predischarge drivers is generally less efficient and can result in requiring larger predriver chains.